The present disclosure relates to semiconductor memory devices, and more particularly to techniques of reducing noise and costs in dynamic random access memories (DRAMs) having a hierarchical bit line architecture. Furthermore, the present disclosure relates to techniques of reducing noise in DRAMs having a hierarchical bit line architecture in which sub bit lines are arranged in a cross-point structure.
In recent years, high integration for providing systems on chip (SoC) at low costs has particularly required in embedded DRAMs. Memory arrays including memory cells and sense amplifier arrays largely occupy the areas of memories. For high integration, miniaturization in memory cell transistors, and memory cell capacitors using high-k films has been employed to reduce the areas of memory cells themselves.
The size reduction ratio of sense amplifier arrays is becoming relatively small as compared to that of memory cell transistors. The reason is as follows. Sense amplifiers need to precisely amplify fine read signals from memories. On the other hand, the sizes of transistors forming a sense amplifier are difficult to reduce, since the reduction causes differences in the electrical characteristics of the transistors to degrade performance. It is thus necessary to increase the number of memory cells which are coupled to a single bit line, and to relatively reduce the number of sense amplifiers in a memory array in order to reduce the area of a memory. Thus, the hierarchical bit line architecture has been focused on to reduce the number of sense amplifiers in each memory array. (See Japanese Patent Publication No. H6-349267, Japanese Patent Publication No. 2007-273851, and Japanese Patent Publication No. 2009-33029.)
On the other hand, a cross-point bit line structure including memory cells at all intersections between word lines and sub bit lines may be employed for high-density integration of the memory cells. A hierarchical bit line architecture is also known, which is formed by combining a cross-point sub bit line structure with a folded main bit line structure including reference bit lines arranged separately from read bit lines to reduce noise. (See Japanese Patent Publication No. S61-217994, Japanese Patent Publication No. H9-171684, and Japanese Patent Publication No. S63-66791.)
In a DRAM having a hierarchical bit line architecture, pitches of sub bit lines in a miniaturizing process are close to the limit in processing. For example, if sub bit lines are formed in a first metal interconnect, main bit lines are formed in a second metal interconnect, which is higher than the first metal interconnect, shunt interconnects of word lines are formed in a third metal interconnect, and global data lines are formed in a fourth metal interconnect.
The number of memory cells, which can be coupled to a single bit line, is determined by the magnitude of a potential difference (i.e., a sensing signal) ΔV caused between the bit line and a complementary bit line when data in a memory cell is read on the bit line. The potential difference ΔV is expressed by the following equation.|ΔV|=(Vdd/2)/((Cbl+Cbm)/Cs+1)In the equation, Vdd represents the power supply voltage of an array, Cbm represents the parasitic capacitance of a main bit line, Cbl represents the parasitic capacitance of a sub bit line, and Cs is the capacitance of a memory cell capacitor. Assume that the hierarchical bit line architecture includes a single main bit line and N sub bit lines, where N is an integer of two or more, which are formed at a lower level than the main bit line. If the expression Cbm<N×Cbl is satisfied, the number of memory cells in each bit line increases N-fold (i.e., the number of the sense amplifiers decreases 1/N-fold), and, at the same time, a sensing signal is greater than that in a non-hierarchical bit line architecture.
In a stacked capacitor DRAM, Cbm is the sum of the parasitic capacitance between a main bit line and a normal surrounding interconnect conductor, and the gate capacitance of a sense amplifier. On the other hand, Cbl additionally includes the parasitic capacitance between an upper electrode and a lower electrode of a memory cell capacitor, which are formed close to the limit under a particular process rule, the junction capacitance of a memory cell transistor, and the overlap capacitance with a word line. As a result, the expression Cbm<Cbl is obtained. Furthermore, the process for a shrinked sub-100-nm embedded DRAM includes the conditions satisfying the expression Cbm<N×Cbl. With the use of a hierarchical bit line architecture, a sensing signal capable of stable operation is obtained while reducing the number of the sense amplifiers.